Semiconductor Duty Stacking: Tracking Tariff Exposure When Your Chip Crosses Four Borders
A single integrated circuit can cross four national borders between wafer start and delivery to your dock. Each crossing involves a different manufacturing stage, a different HTS classification, and potentially a different duty rate. For procurement teams managing semiconductor BOMs with hundreds of line items, cumulative tariff exposure across multi-stage supply chains is one of the most undercounted costs in electronics sourcing.
Four stages, four borders, four tariff events
The typical path for a packaged IC: wafer fabrication in Taiwan or Korea, die preparation and bumping in Japan, packaging at an OSAT in Malaysia or China, and final test either at the same OSAT or at a separate facility in Southeast Asia. Each stage adds value and each stage can trigger a tariff event depending on where the product enters customs.
US import duties apply at the point of entry into the United States. If your finished IC ships directly from a Chinese OSAT to your US facility, the full declared value of the packaged part faces whatever duty rate applies to Chinese-origin goods under its HTS code. Silicon fabricated in Taiwan, die bumped in Japan - none of it reduces the duty. Country of origin follows substantial transformation, and for most ICs the packaging step determines origin.
Two identical dies, fabricated on the same wafer at the same foundry, can carry duty rates 25 percentage points apart based solely on where they were packaged. Die A goes to Penang for packaging and enters the US at MFN rates under HTS 8542. Die B goes to Shanghai and enters at MFN plus 25% Section 301. Same wafer, same design, same electrical specifications - different tariff cost.